...
> > So ending up with (something like):
> > end = buff + length;
> > ...
> > while (++ptr < end) {
> > csum += data;
> > carry += csum < data;
> > data = ptr[-1];
> > }
> > (Although a do-while loop tends to generate better code
> > and gcc will pretty much always make that transformation.)
> >
> > I think that is 4 instructions per word (load, add, cmp+set, add).
> > In principle they could be completely pipelined and all
> > execute (for different loop iterations) in the same clock.
> > (But that is pretty unlikely to happen - even x86 isn't that good.)
> > But taking two clocks is quite plausible.
> > Plus 2 instructions per loop (inc, cmp+jmp).
> > They might execute in parallel, but unrolling once
> > may be required.
> >
> It looks like GCC actually ends up generating 7 total instructions:
> ffffffff808d2acc: 97b6 add a5,a5,a3
> ffffffff808d2ace: 00d7b533 sltu a0,a5,a3
> ffffffff808d2ad2: 0721 add a4,a4,8
> ffffffff808d2ad4: 86be mv a3,a5
> ffffffff808d2ad6: 962a add a2,a2,a0
> ffffffff808d2ad8: ff873783 ld a5,-8(a4)
> ffffffff808d2adc: feb768e3 bltu a4,a1,ffffffff808d2acc <do_csum+0x34>
>
> This mv instruction could be avoided if the registers were shuffled
> around, but perhaps this way reduces some dependency chains.
gcc managed to do 'data += csum' so had add 'csum = data'.
If you unroll once that might go away.
It might then be 10 instructions for 16 bytes.
Although you then need slightly larger alignment code.
David
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