Hi Kuan-Ying,
On Wed, Sep 13, 2023 at 08:11:40AM +0000, Kuan-Ying Lee (李冠穎) wrote:
> On Wed, 2023-08-23 at 14:13 +0100, Alexandru Elisei wrote:
> > diff --git a/arch/arm64/boot/dts/arm/fvp-base-revc.dts
> > b/arch/arm64/boot/dts/arm/fvp-base-revc.dts
> > index 60472d65a355..bd050373d6cf 100644
> > --- a/arch/arm64/boot/dts/arm/fvp-base-revc.dts
> > +++ b/arch/arm64/boot/dts/arm/fvp-base-revc.dts
> > @@ -165,10 +165,28 @@ C1_L2: l2-cache1 {
> > };
> > };
> >
> > - memory@80000000 {
> > + memory0: memory@80000000 {
> > device_type = "memory";
> > - reg = <0x00000000 0x80000000 0 0x80000000>,
> > - <0x00000008 0x80000000 0 0x80000000>;
> > + reg = <0x00 0x80000000 0x00 0x7c000000>;
> > + };
> > +
> > + metadata0: metadata@c0000000 {
> > + compatible = "arm,mte-tag-storage";
> > + reg = <0x00 0xfc000000 0x00 0x3e00000>;
> > + block-size = <0x1000>;
> > + memory = <&memory0>;
> > + };
> > +
> > + memory1: memory@880000000 {
> > + device_type = "memory";
> > + reg = <0x08 0x80000000 0x00 0x7c000000>;
> > + };
> > +
> > + metadata1: metadata@8c0000000 {
> > + compatible = "arm,mte-tag-storage";
> > + reg = <0x08 0xfc000000 0x00 0x3e00000>;
> > + block-size = <0x1000>;
> > + memory = <&memory1>;
> > };
> >
>
> AFAIK, the above memory configuration means that there are two region
> of dram(0x80000000-0xfc000000 and 0x8_80000000-0x8_fc0000000) and this
> is called PDD memory map.
>
> Document[1] said there are some constraints of tag memory as below.
>
> | The following constraints apply to the tag regions in DRAM:
> | 1. The tag region cannot be interleaved with the data region.
> | The tag region must also be above the data region within DRAM.
> |
> | 2.The tag region in the physical address space cannot straddle
> | multiple regions of a memory map.
> |
> | PDD memory map is not allowed to have part of the tag region between
> | 2GB-4GB and another part between 34GB-64GB.
>
> I'm not sure if we can separate tag memory with the above
> configuration. Or do I miss something?
>
> [1] https://developer.arm.com/documentation/101569/0300/?lang=en
> (Section 5.4.6.1)
Good point, thanks. The above dts some random layout we picked as an
example, it doesn't match any real hardware and we didn't pay attention
to the interconnect limitations (we fake the tag storage on the model).
I'll try to dig out how the mtu_tag_addr_shutter registers work and how
the sparse DRAM space is compressed to a smaller tag range. But that's
something done by firmware and the kernel only learns the tag storage
location from the DT (provided by firmware). We also don't need to know
the fine-grained mapping between 32 bytes of data and 1 byte (2 tags) in
the tag storage, only the block size in the tag storage space that
covers all interleaving done by the interconnect (it can be from 1 byte
to something larger like a page; the kernel will then use the lowest
common multiple between a page size and this tag block size to figure
out how many pages to reserve).
--
Catalin
