On 8/1/23 03:53, Alexandre Ghiti wrote: > This series optimizes the tlb flushes on riscv which used to simply > flush the whole tlb whatever the size of the range to flush or the size > of the stride. > > Patch 3 introduces a threshold that is microarchitecture specific and > will very likely be modified by vendors, not sure though which mechanism > we'll use to do that (dt? alternatives? vendor initialization code?). Certainly we would want to set the threshold to zero on SiFive platforms affected by CIP-1200, since they cannot use address-based sfence.vma at all. At least this case could be handled in the existing errata patch function. I don't know about other platforms. Regards, Samuel > > Next steps would be to implement: > - svinval extension as Mayuresh did here [1] > - BATCHED_UNMAP_TLB_FLUSH (I'll wait for arm64 patchset to land) > - MMU_GATHER_RCU_TABLE_FREE > - MMU_GATHER_MERGE_VMAS > > Any other idea welcome. > > [1] https://lore.kernel.org/linux-riscv/20230623123849.1425805-1-mchitale@xxxxxxxxxxxxxxxx/ > > Changes in v3: > - Add RB from Andrew, thanks! > - Unwrap a few lines, as suggested by Andrew > - Introduce defines for -1 constants used in tlbflush.c, as suggested by Andrew and Conor > - Use huge_page_size() directly instead of using the shift, as suggested by Andrew > - Remove misleading comments as suggested by Conor > > Changes in v2: > - Make static tlb_flush_all_threshold, we'll figure out later how to > override this value on a vendor basis, as suggested by Conor and Palmer > - Fix nommu build, as reported by Conor > > Alexandre Ghiti (4): > riscv: Improve flush_tlb() > riscv: Improve flush_tlb_range() for hugetlb pages > riscv: Make __flush_tlb_range() loop over pte instead of flushing the > whole tlb > riscv: Improve flush_tlb_kernel_range() > > arch/riscv/include/asm/tlb.h | 8 ++- > arch/riscv/include/asm/tlbflush.h | 12 ++-- > arch/riscv/mm/tlbflush.c | 98 ++++++++++++++++++++++++++----- > 3 files changed, 99 insertions(+), 19 deletions(-) >
