Hi Alexandre, On Wed, Sep 6, 2023 at 1:01 PM Alexandre Ghiti <alexghiti@xxxxxxxxxxxx> wrote: > > Hi Prabhakar, > > On Wed, Sep 6, 2023 at 1:49 PM Lad, Prabhakar > <prabhakar.csengg@xxxxxxxxx> wrote: > > > > Hi Alexandre, > > > > On Tue, Aug 1, 2023 at 9:58 AM Alexandre Ghiti <alexghiti@xxxxxxxxxxxx> wrote: > > > > > > This function used to simply flush the whole tlb of all harts, be more > > > subtile and try to only flush the range. > > > > > > The problem is that we can only use PAGE_SIZE as stride since we don't know > > > the size of the underlying mapping and then this function will be improved > > > only if the size of the region to flush is < threshold * PAGE_SIZE. > > > > > > Signed-off-by: Alexandre Ghiti <alexghiti@xxxxxxxxxxxx> > > > Reviewed-by: Andrew Jones <ajones@xxxxxxxxxxxxxxxx> > > > --- > > > arch/riscv/include/asm/tlbflush.h | 11 +++++----- > > > arch/riscv/mm/tlbflush.c | 34 +++++++++++++++++++++++-------- > > > 2 files changed, 31 insertions(+), 14 deletions(-) > > > > > After applying this patch, I am seeing module load issues on RZ/Five > > (complete log [0]). I am testing defconfig + [1] (rz/five related > > configs). > > > > Any pointers on what could be an issue here? > > Can you give me the exact version of the kernel you use? The trap > addresses are vmalloc addresses, and a fix for those landed very late > in the release cycle. > I am using next-20230906, Ive pushed a branch [1] for you to have a look. [0] https://github.com/prabhakarlad/linux/tree/rzfive-debug Cheers, Prabhakar
