On Tue, Aug 22, 2023 at 05:34:38PM +0100, Catalin Marinas wrote: > On Wed, Aug 16, 2023 at 07:15:53PM +0100, Mark Brown wrote: > > Right, it's for the GCS memory rather than the registers. I'm fairly > > sure it's excessive but but was erring on the side of caution until I > > have convinced myself that the interactions between GCS barriers and > > regular barriers were doing the right thing, until we have physical > > implementations to contend with I'd guess the practical impact will be > > minimal. > Well, I'd say either we are clear about why it's (not) needed or we ask > the architects to clarify the spec. I haven't checked your latest > series but in principle I don't like adding barriers just because we are > not sure they are needed (and I don't think having hardware eventually > changes this). I should probably also mention that another part of my thinking was that when we implement GCS for EL1 we'll need to ensure that everything is synced during the pivot of the EL1 GCS (each EL needs an independent GCS). We won't be able to rely on having an ERET there so it's going to have more stringent requirements, I was partly punting to think things through fully there.
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