From: Linus Torvalds > Sent: 02 February 2023 19:39 > > On Thu, Feb 2, 2023 at 7:29 AM Peter Zijlstra <peterz@xxxxxxxxxxxxx> wrote: > > > > - fixed up the inline asm to use 'u128 *' mem argument so the compiler knows > > how wide the modification is. > > - reworked the percpu thing to use union based type-punning instead of > > _Generic() based casts. > > Looks lovely to me. This removed all my concerns (except for the > testing one, but all the patches looked nice and clean to me, so > clearly it must be perfect). The change is almost certainly for the better. But did I spot one of the bits using cmpxchg128 just to do an atomic write? I think it was updating some interrupt info that was at first glance not dissimilar to that used by MSI-X (it wasn't MSI-X). If that was a hardware register then it could well require a full bus lock. Using a write of a sse (or equiv) 128bit register would be an atomic write without the bus lock problem. Also, that is only going to work if the hardware/logic side guarantees to treat a single write as atomic. I know there are MSI-X implementations out there where the cpu write will be split into four 32bit writes to some internal memory and the hardware side will also do multiple accesses. (Pretty much any implementation on an fpga will behave like that, not just the one I wrote.) I didn't see the MSI-X code there, but I do wonder how it safely changes affinities. David - Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK Registration No: 1397386 (Wales)
