Jinank!
On Mon, Jan 02 2023 at 07:12, Jinank Jain wrote:
> --- a/arch/x86/include/asm/irq_vectors.h
> +++ b/arch/x86/include/asm/irq_vectors.h
> +/*
> + * FIXME: Change this, once Microsoft Hypervisor changes its assumption
> + * around VMBus interrupt vector allocation for nested root partition.
> + * Or provides a better interface to detect this instead of hardcoding.
> + */
> +#define HYPERV_INTR_NESTED_VMBUS_VECTOR 0x31
arch/x86/include/asm/irq_vectors.h line 47:
/*
* Vectors 0x30-0x3f are used for ISA interrupts.
* round up to the next 16-vector boundary
*/
#define ISA_IRQ_VECTOR(irq) (((FIRST_EXTERNAL_VECTOR + 16) & ~15) + irq)
So this overlaps with the legacy interrupt vector space.
> +#ifdef CONFIG_HYPERV
> + /*
> + * This is a hack because we cannot install this interrupt handler
> + * via alloc_intr_gate as it does not allow interrupt vector less
> + * than FIRST_SYSTEM_VECTORS. And hyperv does not want anything other
> + * than 0x31-0x34 as the interrupt vector for vmbus interrupt in case
> + * of nested setup.
> + */
> + INTG(HYPERV_INTR_NESTED_VMBUS_VECTOR, asm_sysvec_hyperv_nested_vmbus_intr),
> +#endif
I agree, that this is a hack, but that puts it mildly: It's a completely
broken hack.
> +DECLARE_IDTENTRY_SYSVEC(HYPERV_INTR_NESTED_VMBUS_VECTOR, sysvec_hyperv_nested_vmbus_intr);
This generates the low level entry stub for vector 0x31 at compile time,
which competes with the interrupt stub for external interrupts generated
by:
SYM_CODE_START(irq_entries_start)
Now the above INTG() hard-codes the IDT entry for vector 0x31 into the
apic_idts table. That marks it as system vector which in turn prevents
idt_setup_apic_and_irq_gates() to install the IDT entry for the external
vector on _ALL_ systems unconditionally.
IOW, you broke world except for systems which do not use the legacy
interrupt space. Congrats!
That legacy space is hardcoded and that's clearly documented so.
0x31 becomes IRQ1 - usually the i8042 - which makes it pretty much
guaranteed that this collides and fails. The worst case consequence is a
fully uncontrolled interrupt storm which is not even detectable.
So this patch is /dev/null material and either the hypervisor side makes
it possible to use a different vector space or this needs some very
careful modifications to the legacy ISA vector assignment.
Thanks,
tglx
