On Thu, Dec 22, 2022 at 09:26:07PM +0000, Lad, Prabhakar wrote: > Hi Sergey, > > On Thu, Dec 22, 2022 at 9:14 PM Sergey Matyukevich <geomatsi@xxxxxxxxx> wrote: > > > > Hi Prabhakar, > > > > > > > > From: Sergey Matyukevich <sergey.matyukevich@xxxxxxxxxxxxx> > > > > > > > > > > > > Current implementation of update_mmu_cache function performs local TLB > > > > > > flush. It does not take into account ASID information. Besides, it does > > > > > > not take into account other harts currently running the same mm context > > > > > > or possible migration of the running context to other harts. Meanwhile > > > > > > TLB flush is not performed for every context switch if ASID support > > > > > > is enabled. > > > > > > > > > > > > Patch [1] proposed to add ASID support to update_mmu_cache to avoid > > > > > > flushing local TLB entirely. This patch takes into account other > > > > > > harts currently running the same mm context as well as possible > > > > > > migration of this context to other harts. > > > > > > > > > > > > For this purpose the approach from flush_icache_mm is reused. Remote > > > > > > harts currently running the same mm context are informed via SBI calls > > > > > > that they need to flush their local TLBs. All the other harts are marked > > > > > > as needing a deferred TLB flush when this mm context runs on them. > > > > > > > > > > > > [1] https://lore.kernel.org/linux-riscv/20220821013926.8968-1-tjytimi@xxxxxxx/ > > > > > > > > > > > > Signed-off-by: Sergey Matyukevich <sergey.matyukevich@xxxxxxxxxxxxx> > > > > > > --- > > > > > > arch/riscv/include/asm/mmu.h | 2 ++ > > > > > > arch/riscv/include/asm/pgtable.h | 2 +- > > > > > > arch/riscv/include/asm/tlbflush.h | 18 ++++++++++++++++++ > > > > > > arch/riscv/mm/context.c | 10 ++++++++++ > > > > > > arch/riscv/mm/tlbflush.c | 28 +++++++++++----------------- > > > > > > 5 files changed, 42 insertions(+), 18 deletions(-) > > > > > > > > > <snip> > > > > > [ 133.008752] Hardware name: Renesas SMARC EVK based on r9a07g043f01 (DT) > > > > > [ 133.015338] Call Trace: > > > > > [ 133.017778] [<ffffffff800055cc>] dump_backtrace+0x1c/0x24 > > > > > [ 133.023174] [<ffffffff80776836>] show_stack+0x2c/0x38 > > > > > [ 133.028214] [<ffffffff80780244>] dump_stack_lvl+0x3c/0x54 > > > > > [ 133.033597] [<ffffffff80780270>] dump_stack+0x14/0x1c > > > > > [ 133.038633] [<ffffffff80776c00>] panic+0x102/0x29a > > > > > [ 133.043409] [<ffffffff800137ba>] do_exit+0x704/0x70a > > > > > [ 133.048362] [<ffffffff8001390e>] do_group_exit+0x24/0x70 > > > > > [ 133.053659] [<ffffffff8001de54>] get_signal+0x68a/0x6dc > > > > > [ 133.058874] [<ffffffff8000494e>] do_work_pending+0xd6/0x44e > > > > > [ 133.064427] [<ffffffff800036c2>] resume_userspace_slow+0x8/0xa > > > > > [ 133.070249] ---[ end Kernel panic - not syncing: Attempted to kill > > > > > init! exitcode=0x0000000b ]--- > > > > > > > > > > If I revert this patch [0] bonnie++ works as expected. > > > > > > > > > > Any pointers on what could be the issue here? > > > > > > > > > > [0] https://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git/commit/?h=for-next&id=4bd1d80efb5af640f99157f39b50fb11326ce641 > > > > > > > > > > Cheers, > > > > > Prabhakar > > > > > > > > Good catch. Thanks for reporting ! Discussion around the issue and > > > > possible ways to fix it can be found in the following email thread: > > > > > > > > https://lore.kernel.org/linux-riscv/20221111075902.798571-1-guoren@xxxxxxxxxx/ > > > > > > > > Could you please apply the patch from Guo Ren instead of [0] and check > > > > if you have any issues with your test ? Besides, could you please share > > > > your kernel configuration and the actual bonnie++ params from emmc_t_002.sh script ? > > > > > > > Thanks for the pointer, I'll undo my changes and test Guo's patch. > > > > > > I have pasted the script here [0] and attached config. > > > > > > [0] https://paste.debian.net/hidden/a7a769b5/ > > > > Thanks for the script and config. Could you please also share the > > following information: > > - how many cores your system has > The Renesas RZ/Five SoC has a single Andes AX45MP core. > > > - does your system support ASID > > > With a quick look at [0] It does support ASID, unless there is a way > to disable it. > > [0] http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf So you have a single-core system, but your kernel configuration enables CONFIG_SMP. Additional 'deferred TLB flush' logic is dropped at build time if CONFIG_SMP is disabled. On the other hand, system should not fail that way even if SMP is enabled. Let me double-check if anything can go wrong if cpumasks may have only a single cpu. Another suspect is a change in update_mmu_cache: probably making it asid-specific (and thus more granular) was a bad idea. Regards, Sergey
