On Sat, Mar 19, 2022 at 3:27 PM Huacai Chen <chenhuacai@xxxxxxxxxx> wrote: > > LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V. > LoongArch includes a reduced 32-bit version (LA32R), a standard 32-bit > version (LA32S) and a 64-bit version (LA64). LoongArch use ACPI as its > boot protocol LoongArch-specific interrupt controllers (similar to APIC) > are already added in the next revision of ACPI Specification (current > revision is 6.4). > > This patchset is adding basic LoongArch support in mainline kernel, we > can see a complete snapshot here: > https://github.com/loongson/linux/tree/loongarch-next This looks fine to me for the most part, and I only had comments on a couple of things that we we had discussed before. I think the syscall interface and the spinlock implementation bits can be addressed now by leaving the controversial bits out of the submission, but the boot interface still remains to be resolved. As discussed before, I think the best way to do this is to not have a documented custom interface but instead use the UEFI wrapper code for both the (current) ACPI based boot and potential DT based embedded systems that may get added later. Arnd
