On Fri, Oct 08, 2021 at 09:32:58AM -0700, Palmer Dabbelt wrote: > On Thu, 07 Oct 2021 23:54:23 PDT (-0700), boqun.feng@xxxxxxxxx wrote: > > On Fri, Oct 08, 2021 at 04:30:37PM +1100, Michael Ellerman wrote: > > > Boqun Feng <boqun.feng@xxxxxxxxx> writes: > > > > (Add linux-arch in Cc list) > > > > > > > > Architecture maintainers, this patch is about strengthening our memory > > > > model a little bit, your inputs (confirmation, ack/nack, etc.) are > > > > appreciated. > > > > > > Hi Boqun, > > > > > > I don't feel like I'm really qualified to give an ack here, you and the > > > other memory model folk know this stuff much better than me. > > > > > > But I have reviewed it and it matches my understanding of how our > > > barriers work, so it looks OK to me. > > > > > > Reviewed-by: Michael Ellerman <mpe@xxxxxxxxxxxxxx> (powerpc) > > I'm basically in the same spot. I think I said something to that effect > somewhere in the thread, but I'm not sure if it got picked up so > > Acked-by: Palmer Dabbelt <palmerdabbelt@xxxxxxxxxx> (RISC-V) > Thanks! > (I don't feel comfortable reviewing it so I'm acking it, not sure if I'm > just backwards about what all this means though ;)). > > IIUC this change will mean the RISC-V port is broken, but I'm happy to fix No, the RISC-V port is not broken, this patch only strengthen the unlock(A)+lock(B) to TSO ordering, as per the previous discussion: https://lore.kernel.org/lkml/5412ab37-2979-5717-4951-6a61366df0f2@xxxxxxxxxx/ RISC-V's current lock implementation is fine, and it's still OK if RISC-V still to queued spinlock, since as Dan said in that email thread, the following code still provides TSO ordering: FENCE RW, W store A ll/sc B FENCE R, RW Regards, Boqun > it. Were you guys trying to target this for 5.16?
