Hi, Arnd, On Sun, Aug 15, 2021 at 4:56 PM Arnd Bergmann <arnd@xxxxxxxx> wrote: > > On Sat, Aug 14, 2021 at 4:50 AM Huacai Chen <chenhuacai@xxxxxxxxx> wrote: > > On Fri, Aug 13, 2021 at 5:08 PM Arnd Bergmann <arnd@xxxxxxxx> wrote: > > > > > After some thinking, I found that ARM64 is "define kernel VABITS > > depends on page table layout", and MIPS (also LoongArch) is "define > > page table layout depends on kernel VABITS". So you can see: > > > > #ifdef CONFIG_VA_BITS_40 > > #ifdef CONFIG_PAGE_SIZE_4KB > > #define PGD_ORDER 1 > > #define PUD_ORDER aieeee_attempt_to_allocate_pud > > #define PMD_ORDER 0 > > #define PTE_ORDER 0 > > #endif > > I have no idea what aieeee_attempt_to_allocate_pud means, but > this part seems fine. It just used to avoid kernel use PUD_ORDER. > > > #ifdef CONFIG_PAGE_SIZE_16KB > > #define PGD_ORDER 0 > > #define PUD_ORDER aieeee_attempt_to_allocate_pud > > #define PMD_ORDER 0 > > #define PTE_ORDER 0 > > #endif > > This doesn't seem to make sense at all however: it looks like you have > three levels of 16KB page tables, so you get 47 bits, not 40. This > means you waste 99% of the available address space when you > run this kernel on a CPU that is able to access the entire space. Emm, this "waste" seems harmless. :) > > > #ifdef CONFIG_PAGE_SIZE_64KB > > #define PGD_ORDER 0 > > #define PUD_ORDER aieeee_attempt_to_allocate_pud > > #define PMD_ORDER aieeee_attempt_to_allocate_pmd > > #define PTE_ORDER 0 > > #endif > > #endif > > Similarly, here it seems you get 42 bits. > > > #ifdef CONFIG_VA_BITS_48 > > #ifdef CONFIG_PAGE_SIZE_4KB > > #define PGD_ORDER 0 > > #define PUD_ORDER 0 > > #define PMD_ORDER 0 > > #define PTE_ORDER 0 > > #endif > > #ifdef CONFIG_PAGE_SIZE_16KB > > #define PGD_ORDER 1 > > #define PUD_ORDER aieeee_attempt_to_allocate_pud > > #define PMD_ORDER 0 > > #define PTE_ORDER 0 > > #endif > > This again looks reasonable, though I don't see why you care about > having the extra pgd_order here, instead of just going with > 47 bits. > > > #ifdef CONFIG_PAGE_SIZE_64KB > > #define PGD_ORDER 0 > > #define PUD_ORDER aieeee_attempt_to_allocate_pud > > #define PMD_ORDER 0 > > #define PTE_ORDER 0 > > #endif > > #endif > > I suppose you can't ever have more than 48 bits? Otherwise this option > would give you 55 bits of address space. We will have 56bits CPU in future, and then we will add a VA_BITS_56 config. > > > Since 40 and 48 is the most popular VABITS of LoongArch hardware, and > > LoongArch has a software-managed TLB, it seems "define page table > > layout depends on kernel VABITS" is more natural for LoongArch. > > How common are Loongarch64 CPUs that limit the virtual address space > to 40 bits instead of the full 48 bits? What is the purpose of limiting the > CPU this way? We have some low-end 64bits CPU whose VA is 40bits, this can reduce the internal address bus width, so save some hardware cost and complexity. Huacai > > Arnd
