Hi Rui,
On Wed, Jul 28, 2021 at 1:50 PM Rui Wang <wangrui@xxxxxxxxxxx> wrote:
> From: wangrui <wangrui@xxxxxxxxxxx>
>
> This patch introduce a new atomic primitive 'and_or', It may be have three
> types of implemeations:
>
> * The generic implementation is based on arch_cmpxchg.
> * The hardware supports atomic 'and_or' of single instruction.
> * The hardware supports LL/SC style atomic operations:
>
> 1: ll v1, mem
> and t1, v1, arg1
> or t1, t1, arg2
> sc t1, mem
> beq t1, 0, 1b
>
> Now that all the architectures have implemented it.
>
> Signed-by-off: Rui Wang <wangrui@xxxxxxxxxxx>
> Signed-by-off: hev <r@xxxxxx>
> --- a/arch/m68k/include/asm/atomic.h
> +++ b/arch/m68k/include/asm/atomic.h
> @@ -67,6 +67,22 @@ static inline int arch_atomic_fetch_##op(int i, atomic_t *v) \
> return tmp; \
> }
>
> +#define ATOMIC_FETCH_OP2(op, c_op1, c_op2, asm_op1, asm_op2) \
> +static inline int arch_atomic_fetch_##op(int i, int j, atomic_t *v) \
> +{ \
> + int t, tmp; \
> + \
> + __asm__ __volatile__( \
> + "1: movel %2,%1\n" \
> + " " #asm_op1 "l %3,%1\n" \
> + " " #asm_op2 "l %4,%1\n" \
> + " casl %2,%1,%0\n" \
> + " jne 1b" \
> + : "+m" (*v), "=&d" (t), "=&d" (tmp) \
> + : "g" (i), "g" (j), "2" (arch_atomic_read(v))); \
"di" (i), "di" (j)
cfr. "[PATCH v2] m68k: Fix asm register constraints for atomic ops"
https://lore.kernel.org/linux-m68k/20210809112903.3898660-1-geert@xxxxxxxxxxxxxx/
> + return tmp; \
> +}
> +
> #else
>
> #define ATOMIC_OP_RETURN(op, c_op, asm_op) \
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
