On Wed, Jul 07, 2021 at 11:56:37PM +1000, Nicholas Piggin wrote: > Excerpts from Peter Zijlstra's message of July 6, 2021 9:06 pm: > > On Tue, Jul 06, 2021 at 12:18:07PM +0800, Huacai Chen wrote: > >> + .align 5 /* 32 byte rollback region */ > >> +SYM_FUNC_START(__arch_cpu_idle) > >> + /* start of rollback region */ > >> + LONG_L t0, tp, TI_FLAGS > >> + nop > >> + andi t0, t0, _TIF_NEED_RESCHED > >> + bnez t0, 1f > >> + nop > >> + nop > >> + nop > >> + idle 0 > >> + /* end of rollback region */ > >> +1: > >> + jirl zero, ra, 0 > >> +SYM_FUNC_END(__arch_cpu_idle) > > > >> +/* > >> + * Common Vectored Interrupt > >> + * Complete the register saves and invoke the do_vi() handler > >> + */ > >> +SYM_FUNC_START(except_vec_vi_handler) > >> + la t1, __arch_cpu_idle > >> + LONG_L t0, sp, PT_EPC > >> + /* 32 byte rollback region */ > >> + ori t0, t0, 0x1f > >> + xori t0, t0, 0x1f > >> + bne t0, t1, 1f > >> + LONG_S t0, sp, PT_EPC > > > > Seriously, you're having your interrupt handler recover from the idle > > race? On a *new* architecture? > > It's heavily derived from MIPS (does that make the wholesale replacement > of arch/mips copyright headers a bit questionable?). > > I don't think it's such a bad trick though -- restartable sequences > before they were cool. It can let you save an irq disable in some > cases (depending on the arch of course). In this case you're making *every* interrupt slower. Simply adding a new idle instruction, one that can be called with interrupts disabled and will terminate on a pending interrupt, would've solved the issues much nicer and reclaimed the cycles spend on this restart trick.
