On Tue, Jul 27, 2021 at 01:03:32AM +0800, Boqun Feng wrote: > I'm missing you point here, a) ll/sc can provide forward progress and b) > ll/sc instructions are used to implement xchg/cmpxchg (see ARM64 and > PPC). Correct on both counts, but b) is tricky, even if a), then it doesn't hold that the primitive resulting from b) also provides fwd progress. I feel this point is often overlooked. I should go add something to atomic_t.txt about that I suppose. > > How to make CPU guarantee "load + cmpxchg" forward-progress? Fusion > > these instructions and lock the snoop channel? > > Maybe hardware guys would think that it's easier to implement cas + > > dcas + amo(short & byte). > > > > Please note that if _Q_PENDING_BITS == 1, then the xchg_tail() is > implemented as a "load + cmpxchg", so if "load + cmpxchg" implementation > of xchg16() doesn't provide forward-progress in an architecture, neither > does xchg_tail(). Right, so generally we rely on cmpxchg() to provide fairness. Some architectures (notably Sparc64) go to great lengths to ensure this. I have memories of adding backoff to an LL/SC based arch at some point, but I cannot find it in a hurry, so it could be one of the since deleted archs.
