On Tue, Jul 6, 2021 at 6:18 AM Huacai Chen <chenhuacai@xxxxxxxxxxx> wrote:
> +
> +#ifdef ARCH_HAS_USABLE_BUILTIN_POPCOUNT
> +
> +#include <asm/types.h>
> +
> +static inline unsigned int __arch_hweight32(unsigned int w)
> +{
> + return __builtin_popcount(w);
> +}
This looks like you incorrect copied it from MIPS: For a new architecture,
you should know whether __builtin_popcount is usable or not.
> +static inline unsigned long __xchg(volatile void *ptr, unsigned long x,
> + int size)
> +{
> + switch (size) {
> + case 1:
> + case 2:
> + return __xchg_small(ptr, x, size);
If there is no native sub-word xchg(), then better make this BUILD_BUG(),
see the riscv implementation.
> +
> +static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
> + unsigned long new, unsigned int size)
> +{
> + switch (size) {
> + case 1:
> + case 2:
> + return __cmpxchg_small(ptr, old, new, size);
Same here.
> +++ b/arch/loongarch/include/asm/fb.h
> @@ -0,0 +1,23 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2020-2021 Loongson Technology Corporation Limited
> + */
> +#ifndef _ASM_FB_H_
> +#define _ASM_FB_H_
> +
> +#include <linux/fb.h>
> +#include <linux/fs.h>
> +#include <asm/page.h>
> +
> +static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
> + unsigned long off)
> +{
> + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
> +}
Do you have a writethrough or write-combine map type? noncached makes
this slower than necessary.
> +/*
> + * On LoongArch I/O ports are memory mapped, so we access them using normal
> + * load/store instructions. loongarch_io_port_base is the virtual address to
> + * which all ports are being mapped. For sake of efficiency some code
> + * assumes that this is an address that can be loaded with a single lui
> + * instruction, so the lower 16 bits must be zero. Should be true on any
> + * sane architecture; generic code does not use this assumption.
> + */
> +extern unsigned long loongarch_io_port_base;
> +
> +static inline void set_io_port_base(unsigned long base)
> +{
> + loongarch_io_port_base = base;
> +}
If you are able to map this to a fixed virtual address (in fixmap or elsewhere),
you can just use the asm-generic version.
> +/*
> + * ISA I/O bus memory addresses are 1:1 with the physical address.
> + */
> +static inline unsigned long isa_virt_to_bus(volatile void *address)
> +{
> + return virt_to_phys(address);
> +}
> +
> +static inline void *isa_bus_to_virt(unsigned long address)
> +{
> + return phys_to_virt(address);
> +}
> +/*
> + * However PCI ones are not necessarily 1:1 and therefore these interfaces
> + * are forbidden in portable PCI drivers.
> + *
> + * Allow them for x86 for legacy drivers, though.
> + */
> +#define virt_to_bus virt_to_phys
> +#define bus_to_virt phys_to_virt
As mentioned in another patch, these should not exist on new architectures.
> +
> +static inline void __iomem *ioremap_prot(phys_addr_t offset, unsigned long size,
> + unsigned long prot_val)
> +{
> + /* This only works for !HIGHMEM currently */
Do you support highmem? I would expect new architectures to no longer
implement that. Just use a 64-bit kernel on systems with lots of ram.
> +#define ioremap(offset, size) \
> + ioremap_prot((offset), (size), _CACHE_SUC)
> +#define ioremap_uc ioremap
Remove ioremap_uc(), it should never be called here.
> +/*
> + * ioremap_wc - map bus memory into CPU space
> + * @offset: bus address of the memory
> + * @size: size of the resource to map
> + *
> + * ioremap_wc performs a platform specific sequence of operations to
> + * make bus memory CPU accessible via the readb/readw/readl/writeb/
> + * writew/writel functions and the other mmio helpers. The returned
> + * address is not guaranteed to be usable directly as a virtual
> + * address.
> + *
> + * This version of ioremap ensures that the memory is marked uncachable
> + * but accelerated by means of write-combining feature. It is specifically
> + * useful for PCIe prefetchable windows, which may vastly improve a
> + * communications performance. If it was determined on boot stage, what
> + * CPU CCA doesn't support WUC, the method shall fall-back to the
> + * _CACHE_SUC option (see cpu_probe() method).
> + */
> +#define ioremap_wc(offset, size) \
> + ioremap_prot((offset), (size), boot_cpu_data.writecombine)
It seems this is all copied from MIPS again. Are you sure you need to support
both versions with a runtime conditional?
> +#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type) \
> + \
> +static inline void pfx##write##bwlq(type val, \
> + volatile void __iomem *mem) \
> +{ \
Please don't add another copy of these macros. Use the version from
include/asm-generic, or modify it as needed if it doesn't quite work.
> diff --git a/arch/loongarch/include/asm/vga.h b/arch/loongarch/include/asm/vga.h
> new file mode 100644
> index 000000000000..eef95f2f837a
> --- /dev/null
> +++ b/arch/loongarch/include/asm/vga.h
> @@ -0,0 +1,56 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Access to VGA videoram
> + *
> + * Copyright (C) 2020-2021 Loongson Technology Corporation Limited
> + */
I think it would be better not to support VGA console, but to use the EFI
framebuffer.
> diff --git a/arch/loongarch/kernel/cmpxchg.c b/arch/loongarch/kernel/cmpxchg.c
> new file mode 100644
> index 000000000000..30f9f1ee4f0a
> --- /dev/null
> +++ b/arch/loongarch/kernel/cmpxchg.c
> @@ -0,0 +1,100 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Author: Huacai Chen <chenhuacai@xxxxxxxxxxx>
> + * Copyright (C) 2020-2021 Loongson Technology Corporation Limited
> + */
> +
> +#include <linux/bitops.h>
> +#include <asm/cmpxchg.h>
> +
> +unsigned long __xchg_small(volatile void *ptr, unsigned long val, unsigned int size)
> +{
This file should not be there, I think you just copied it from the MIPS version.
Which brings me to an important point: anything you copied from elsewhere
is clearly not copyrighted by Loongson. I think you need to go through each
file and update the copyright and author statements to reflect who actually
wrote the code. At least you won't have to update this file if you remove it ;-)
Arnd
