On Tue, Jul 6, 2021 at 6:18 AM Huacai Chen <chenhuacai@xxxxxxxxxxx> wrote: > > LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V. > LoongArch includes a reduced 32-bit version (LA32R), a standard 32-bit > version (LA32S) and a 64-bit version (LA64). LoongArch use ACPI as its > boot protocol LoongArch-specific interrupt controllers (similar to APIC) > are already added in the next revision of ACPI Specification (current > revision is 6.4). > > This patchset is adding basic LoongArch support in mainline kernel, we > can see a complete snapshot here: > https://github.com/loongson/linux/tree/loongarch-next > > Cross-compile tool chain to build kernel: > https://github.com/loongson/build-tools/releases > > Loongson and LoongArch documentations: > https://github.com/loongson/LoongArch-Documentation > > LoongArch-specific interrupt controllers: > https://mantis.uefi.org/mantis/view.php?id=2203 Thanks a lot for your submission, I've been waiting for this, and have just completed an initial quick review, will send out the individual replies in a bit. I have a few high-level comments about things that need to be improved before merging: 1. Copyright statements: I can see that you copied a lot of code from arch/mips, and then a bit from arch/arm64 and possibly arch/riscv/, but every file just lists loongson as the copyright holder and one or more employees as authors. This clearly has to be resolved by listing the original authors as well. 2. Reducing the amount of copied code: my impression is that the bits you wrote yourself are generally of higher quality than the bits you copied from mips, usually because those have grown over a long time to accommodate cases you should not worry about. In cases where there was no generic implementation, we should try to come up with a version that can be shared instead of adding another copy. 3. 32-bit support: There are small bits of code for 32-bit support everywhere throughout the code base, but there is also code that does not look like it would work in that configuration. I would suggest you split out all 32-bit code into a separate patch, the way you have done for SMP and NUMA support. That way it can be reviewed separately, or deferred until when you actually add support for a 32-bit platform. Please also clarify which modes you plan to support: should every 64-bit kernel be able to run LA32R and LA32S user space binaries, or do you require running the same instruction set in both kernel and user space as RISC-V does? Do you plan to have MIPS N32 style user space on 64-bit kernels? 4. Toolchain sources: I see you only have binaries for an older gcc-8.3 release and no sources so far. I assume you are already busy porting the internal patches to the latest gcc and will post that soon, but my feeling is that the kernel port should not get merged until we have a confirmation from the toolchain maintainers that they plan to merge support for their following release. We should however make sure that your kernel port is completely reviewed and can just get merged once we get there. 5. Platform support: You have copied the underlying logic from arch/mips, but that still uses a method where most platforms (not the new "generic" version) are mutually exclusive. Since you only support one platform right now, it would be best to just simplify it to the point where no platform specific code is needed in arch/loongarch/ and it just works. If you add 32-bit support later on, that obviously requires making a choice between two or three incompatible options. Arnd
