On Thu, Jun 17, 2021 at 11:30 PM David Laight <David.Laight@xxxxxxxxxx> wrote: > > From: Matteo Croce > > Sent: 16 June 2021 19:52 > > To: Guo Ren <guoren@xxxxxxxxxx> > > > > On Wed, Jun 16, 2021 at 1:46 PM Guo Ren <guoren@xxxxxxxxxx> wrote: > > > > > > Hi Matteo, > > > > > > Have you tried Glibc generic implementation code? > > > ref: https://lore.kernel.org/linux-arch/20190629053641.3iBfk9- > > I_D29cDp9yJnIdIg7oMtHNZlDmhLQPTumhEc@z/#t > > > > > > If Glibc codes have the same performance in your hardware, then you > > > could give a generic implementation first. > > Isn't that a byte copy loop - the performance of that ought to be terrible. > ... > > > I had a look, it seems that it's a C unrolled version with the > > 'register' keyword. > > The same one was already merged in nios2: > > https://elixir.bootlin.com/linux/latest/source/arch/nios2/lib/memcpy.c#L68 > > I know a lot about the nios2 instruction timings. > (I've looked at code execution in the fpga's intel 'logic analiser.) > It is a very simple 4-clock pipeline cpu with a 2-clock delay > before a value read from 'tightly coupled memory' (aka cache) > can be used in another instruction. > There is also a subtle pipeline stall if a read follows a write > to the same memory block because the write is executed one > clock later - and would collide with the read. > Since it only ever executes one instruction per clock loop > unrolling does help - since you never get the loop control 'for free'. > OTOH you don't need to use that many registers. > But an unrolled loop should approach 2 bytes/clock (32bit cpu). > > > I copied _wordcopy_fwd_aligned() from Glibc, and I have a very similar > > result of the other versions: > > > > [ 563.359126] Strings selftest: memcpy(src+7, dst+7): 257 Mb/s > > What clock speed is that running at? > It seems very slow for a 64bit cpu (that isn't an fpga soft-cpu). > > While the small riscv cpu might be similar to the nios2 (and mips > for that matter), there are also bigger/faster cpu. > I'm sure these can execute multiple instructions/clock > and possible even read and write at the same time. > Unless they also support significant instruction re-ordering > the trivial copy loops are going to be slow on such cpu. > It's running at 1 GHz. I get 257 Mb/s with a memcpy, a bit more with a memset, but I get 1200 Mb/s with a cyle which just reads memory with 64 bit addressing. -- per aspera ad upstream
