Hi,
Thanks for the patches
On Sun, Jun 06, 2021 at 09:04:07AM +0000, guoren@xxxxxxxxxx wrote:
> From: Guo Ren <guoren@xxxxxxxxxxxxxxxxx>
>
> Add initial DTS for Allwinner D1 NeZha board having only essential
> devices (uart, dummy, clock, reset, clint, plic, etc).
>
> Signed-off-by: Guo Ren <guoren@xxxxxxxxxxxxxxxxx>
> Co-Developed-by: Liu Shaohua <liush@xxxxxxxxxxxxxxxxx>
> Signed-off-by: Liu Shaohua <liush@xxxxxxxxxxxxxxxxx>
> Cc: Anup Patel <anup.patel@xxxxxxx>
> Cc: Atish Patra <atish.patra@xxxxxxx>
> Cc: Christoph Hellwig <hch@xxxxxx>
> Cc: Chen-Yu Tsai <wens@xxxxxxxx>
> Cc: Drew Fustini <drew@xxxxxxxxxxxxxxx>
> Cc: Maxime Ripard <maxime@xxxxxxxxxx>
> Cc: Palmer Dabbelt <palmerdabbelt@xxxxxxxxxx>
> Cc: Wei Fu <wefu@xxxxxxxxxx>
> Cc: Wei Wu <lazyparser@xxxxxxxxx>
> ---
> arch/riscv/boot/dts/Makefile | 1 +
> arch/riscv/boot/dts/allwinner/Makefile | 2 +
> .../boot/dts/allwinner/allwinner-d1-nezha-kit.dts | 29 ++++++++
> arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi | 84 ++++++++++++++++++++++
Can you add the riscv folder to our MAINTAINERS entry as well?
> 4 files changed, 116 insertions(+)
> create mode 100644 arch/riscv/boot/dts/allwinner/Makefile
> create mode 100644 arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts
> create mode 100644 arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi
>
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> index fe996b8..3e7b264 100644
> --- a/arch/riscv/boot/dts/Makefile
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -2,5 +2,6 @@
> subdir-y += sifive
> subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
> subdir-y += microchip
> +subdir-y += allwinner
I assume they should be ordered alphabetically?
> obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
> diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/allwinner/Makefile
> new file mode 100644
> index 00000000..4adbf4b
> --- /dev/null
> +++ b/arch/riscv/boot/dts/allwinner/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_SOC_SUNXI) += allwinner-d1-nezha-kit.dtb
> diff --git a/arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts b/arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts
> new file mode 100644
> index 00000000..cd9f7c9
> --- /dev/null
> +++ b/arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts
> @@ -0,0 +1,29 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +
> +/dts-v1/;
> +
> +#include "allwinner-d1.dtsi"
> +
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + model = "Allwinner D1 NeZha Kit";
> + compatible = "allwinner,d1-nezha-kit";
> +
> + chosen {
> + bootargs = "console=ttyS0,115200";
> + stdout-path = &serial0;
> + };
> +
> + memory@40000000 {
> + device_type = "memory";
> + reg = <0x0 0x40000000 0x0 0x20000000>;
> + };
> +
> + soc {
> + };
> +};
> +
> +&serial0 {
> + status = "okay";
> +};
> diff --git a/arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi b/arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi
> new file mode 100644
> index 00000000..11cd938
> --- /dev/null
> +++ b/arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi
> @@ -0,0 +1,84 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +
> +/dts-v1/;
> +
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + model = "Allwinner D1 Soc";
> + compatible = "allwinner,d1-nezha-kit";
> +
> + chosen {
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = <2400000>;
> + cpu@0 {
> + device_type = "cpu";
> + reg = <0>;
> + status = "okay";
> + compatible = "riscv";
> + riscv,isa = "rv64imafdcv";
> + mmu-type = "riscv,sv39";
> + cpu0_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + };
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "simple-bus";
> + ranges;
> +
> + reset: reset-sample {
> + compatible = "thead,reset-sample";
> + plic-delegate = <0x0 0x101ffffc>;
> + };
This compatible is not documented anywhere?
Maxime
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