Στις 2021-06-06 12:04, guoren@xxxxxxxxxx έγραψε:
From: Guo Ren <guoren@xxxxxxxxxxxxxxxxx> The dma-noncoherent SOCs need different virtual memory mappings with different attributes: - noncached + Strong Order (for IO/DMA descriptor) - noncached + Weak Order (for writecombine usage, eg: frame buffer) All above base on PTE attributes by MMU hardware. That means address attributes are determined by PTE entry, not PMA. RISC-V soc vendors have defined their own custom PTE attributes for dma-noncoherency.
This patch violates the Privilege Spec section 4.4.1 that clearly states:
"Bits63–54 are reserved for future standard use and must be zeroed by software for forward compatibility"
Standard use means that valid values can only be defined by the Priv. Spec, not by the vendor (otherwise they'd be marked as "custom use" or "platform use"), and since they "must" be zeroed by software we 'll be violating the Privilege Spec if we do otherwise.
