On Wed, Apr 7, 2021 at 6:00 PM Peter Zijlstra <peterz@xxxxxxxxxxxxx> wrote: > > On Wed, Apr 07, 2021 at 04:29:12PM +0200, Christoph Müllner wrote: > > RISC-V defines LR/SC loops consisting of up to 16 instructions as > > constrained LR/SC loops. Such constrained LR/SC loops provide the > > required forward guarantees, that are expected (similar to what other > > architectures, like AArch64, have). > > The text quoted by others didn't seem to say such a thing, but whatever. The RISC-V unpriv spec is public can be found here: https://riscv.org/technical/specifications/ Version 20191213 discusses LR/SC-loops in section 8.3 (page 51). So in case you are interested in the exact wording, you can find it there. > > What RISC-V does not have is sub-word atomics and if required, we > > would have to implement them as LL/SC sequences. And yes, using atomic > > instructions is preferred over using LL/SC, > > (psudo asm, can't be bothered to figure out the actual syntax) > > # setup r_and_mask, r_or_mask > > .L1 > LL r, [word] > AND r, r, r_and_mask > OR r, r, r_or_mask > SC r, [word] > JNE .L1 I fully agree with this. I've implemented a patch for that two weeks ago using the following helper: +/* + * Mask and set given bits at a given address atomically. + * The masked old value will be returned. + */ +static inline u32 atomic_mask_and_set(u32* p, u32 mask, u32 val) +{ + u32 ret, tmp; + __asm__ __volatile__ ( + "0: lr.w %0, %2\n" + " and %0, %0, %3\n" + " or %1, %0, %4\n" + " sc.w %1, %1, %2\n" + " bnez %1, 0b\n" + : "+&r"(ret), "=&r" (tmp), "+A"(*p) + : "r" (mask), "rJ"(val) + : "memory"); + return ret; +} However, Guo pushed out a new patchset in between and I decided to not continue my approach to not undermine his approach. I will sync up with Guo to provide a common patchset. Thanks, Christoph > is what you need for LL/SC based xchg16, that's less than 16 > instructions. If RISC-V guarantees fwd progress on that, good, write it > like that and lets end this thread. > > The fact that this is apparently hard, is not good.
