Hi, These patches provide generic infrastructure to determine TLB page size from page table entries alone. Perf will use this (for either data or code address) to aid in profiling TLB issues. While most architectures only have page table aligned large pages, some (notably ARM64, Sparc64 and Power) provide non page table aligned large pages and need to provide their own implementation of these functions. I've provided (completely untested) implementations for ARM64, Sparc64 and Power/8xxx (it looks like I'm still missing Power/Book3s64/hash support). Changes since -v1: - Changed wording to reflect these are page-table sizes; actual TLB sizes might vary. - added Power/8xx Barring any objections I'll queue these in tip/perf/core, as these patches fix the code that's currently in there.
