On Fri, Nov 13, 2020 at 12:19:01PM +0100, Peter Zijlstra wrote: > Hi, > > These patches provide generic infrastructure to determine TLB page size from > page table entries alone. Perf will use this (for either data or code address) > to aid in profiling TLB issues. I'm not sure it's an issue, but strictly speaking, size of page according to page table tree doesn't mean pagewalk would fill TLB entry of the size. CPU may support 1G pages in page table tree without 1G TLB at all. IIRC, current Intel CPU still don't have any 1G iTLB entries and fill 2M iTLB instead. -- Kirill A. Shutemov
