On 5/5/20 2:19 AM, Mike Rapoport wrote: > From the code I've got the impression that it is either one of them. I.e > the physical memory is either at > > 0x8000_0000 - <end of DDR 0 bank> > 0x0000_0000 - <end of DDR 1 bank> > > or > > 0x0_8000_0000 - <end of DDR 0 bank> > 0x1_0000_0000 - <end of DDR 1 bank> > > Is this possible to have a system with three live ranges? Like > > 0x0_0000_0000 - <end of DDR 1 bank> > 0x0_8000_0000 - <end of DDR 0 bank> > 0x1_0000_0000 - <end of DDR 2 bank> We don't have such a system, but it is indeed possible in theory. The question is - Can other arches have such a setup too - Is it not better to have the core retain the flexibility just in case Thx, -Vineet
