On Wed, Dec 11, 2019 at 08:31:28PM +0100, Arnd Bergmann wrote:
> On Wed, Dec 11, 2019 at 7:40 PM Catalin Marinas <catalin.marinas@xxxxxxx> wrote:
> >
> > From: Vincenzo Frascino <vincenzo.frascino@xxxxxxx>
> >
> > Add MTE-specific SIGSEGV codes to siginfo.h.
> >
> > Note that the for MTE we are reusing the same SPARC ADI codes because
> > the two functionalities are similar and they cannot coexist on the same
> > system.
> >
> > Cc: Arnd Bergmann <arnd@xxxxxxxx>
> > Signed-off-by: Vincenzo Frascino <vincenzo.frascino@xxxxxxx>
> > [catalin.marinas@xxxxxxx: renamed precise/imprecise to sync/async]
> > Signed-off-by: Catalin Marinas <catalin.marinas@xxxxxxx>
> > ---
> > include/uapi/asm-generic/siginfo.h | 9 +++++++--
> > 1 file changed, 7 insertions(+), 2 deletions(-)
> >
> > diff --git a/include/uapi/asm-generic/siginfo.h b/include/uapi/asm-generic/siginfo.h
> > index cb3d6c267181..a5184a5438c6 100644
> > --- a/include/uapi/asm-generic/siginfo.h
> > +++ b/include/uapi/asm-generic/siginfo.h
> > @@ -227,8 +227,13 @@ typedef struct siginfo {
> > # define SEGV_PKUERR 4 /* failed protection key checks */
> > #endif
> > #define SEGV_ACCADI 5 /* ADI not enabled for mapped object */
> > -#define SEGV_ADIDERR 6 /* Disrupting MCD error */
> > -#define SEGV_ADIPERR 7 /* Precise MCD exception */
> > +#ifdef __aarch64__
> > +# define SEGV_MTEAERR 6 /* Asynchronous MTE error */
> > +# define SEGV_MTESERR 7 /* Synchronous MTE exception */
> > +#else
> > +# define SEGV_ADIDERR 6 /* Disrupting MCD error */
> > +# define SEGV_ADIPERR 7 /* Precise MCD exception */
> > +#endif
>
> SEGV_ADIPERR/SEGV_ADIDERR were added together with SEGV_ACCADI,
> it seems a bit odd to make only two of them conditional but not the others.
Ah, I missed this. I think we should drop the #ifdef entirely. There is
no harm in having two different macros with the same value.
> I think we are generally working towards having the same constants
> across architectures even for features that only exist on one of them.
I'd rather keep both the ARM and SPARC naming here as the behaviour may
be subtly different between the two architectures. IIUC, the disrupting
SPARC MCD error on means a memory corruption trap sent to the
hypervisor. On ARM MTE, the asynchronous tag check fault is a pretty
much benign setting of a status flag. The kernel, when detecting this
flag, injects a SIGSEGV on the ret_to_user path. If there's no switch
into the kernel, a user program cannot become aware of the asynchronous
MTE tag check fault.
We also don't have the equivalent of ACCADI.
--
Catalin
