On Thu, Jun 20, 2019 at 06:34:29PM +0000, Eugeniy Paltsev wrote: > On Wed, 2019-06-19 at 10:12 +0200, Peter Zijlstra wrote: > > On Tue, Jun 18, 2019 at 04:16:20PM +0000, Vineet Gupta wrote: > > I'm assuming you've looked at what x86 currently does and found > > something like that doesn't work for ARC? > > To be honest I've mostly look at arm/arm64 implementation :) Yeah, but that's fixed instruction width RISC. They have it easy.
