On Thu, 2018-08-30 at 10:19 -0700, Dave Hansen wrote: > On 08/30/2018 09:23 AM, Jann Horn wrote: > > > > Three threads (A, B, C) run with the same CR3. > > > > 1. a dirty+writable PTE is placed directly in front of B's shadow > > stack. > > (this can happen, right? or is there a guard page?) > > 2. C's TLB caches the dirty+writable PTE. > > 3. A performs some syscall that triggers ptep_set_wrprotect(). > > 4. A's syscall calls clear_bit(). > > 5. B's TLB caches the transient shadow stack. > > [now C has write access to B's transiently-extended shadow stack] > > 6. B recurses into the transiently-extended shadow stack > > 7. C overwrites the transiently-extended shadow stack area. > > 8. B returns through the transiently-extended shadow stack, giving > > the attacker instruction pointer control in B. > > 9. A's syscall broadcasts a TLB flush. > Heh, that's a good point. The shadow stack permissions are *not* > strictly reduced because a page getting marked as shadow-stack has > *increased* permissions when being used as a shadow stack. Fun. > > For general hardening, it seems like we want to ensure that there's > a > guard page at the bottom of the shadow stack. Yu-cheng, do we have > a > guard page? We don't have the guard page now, but there is a shadow stack token there, which cannot be used as a return address. Yu-cheng
