On Wed, Aug 22, 2018 at 03:56:28PM -0400, Mikulas Patocka wrote: > > > On Wed, 22 Aug 2018, Sinan Kaya wrote: > > > On 8/22/2018 1:47 PM, Mikulas Patocka wrote: > > > If ARM guarantees that the accesses to a given device are not reordered - > > > then the barriers in readl and writel are superfluous. > > > > It is not. ARM only guarantees ordering of read/write transactions targeting > > a device not memory. > > > > example: > > > > write memory > > raw write to device > > > > or > > > > raw read from device > > read memory > > > > these can bypass each other on ARM unless a barrier is placed in the right > > place either via readl()/writel() or explicitly. > > Yes - but - why does Linux insert the barriers into readl() and writel() > instead of inserting them between accesses to registers and memory? > > A lot of drivers have long sequences of accesses to memory-mapped > registers with no interleaving accesses to coherent memory and these > implicit barriers slow them down with no gain at all. That's what readX_relaxed and writeX_relaxed are for. There was some discussion on the lists a way back, and Torvalds was very clear that readX and writeX should follow the x86 semantics, which have these ordering guarantees against accesses to memory. Will
