On Sun, 22 Apr 2018 09:05:21 +0100, Pavel Machek wrote: > > Hi! > > > @@ -205,6 +205,14 @@ Before jumping into the kernel, the following conditions must be met: > > ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b0. > > - The DT or ACPI tables must describe a GICv2 interrupt controller. > > > > + For CPUs with pointer authentication functionality: > > + - If EL3 is present: > > + SCR_EL3.APK (bit 16) must be initialised to 0b1 > > + SCR_EL3.API (bit 17) must be initialised to 0b1 > > + - If the kernel is entered at EL1: > > + HCR_EL2.APK (bit 40) must be initialised to 0b1 > > + HCR_EL2.API (bit 41) must be initialised to 0b1 > > + > > 0b1 is quite confusing way to write 1. Do you find 0x1 equally confusing? 0bx is a pretty common way of describing bit-fields of a hardware register. It is also consistent with the rest of this document. M. -- Jazz is not dead, it just smell funny.
