On 3/15/2018 8:46 PM, Mark Rutland wrote:
On Thu, Mar 15, 2018 at 06:55:32PM +0530, Chintan Pandya wrote:
On 3/15/2018 6:43 PM, Mark Rutland wrote:
On Thu, Mar 15, 2018 at 06:15:04PM +0530, Chintan Pandya wrote:
Huge mapping changes PMD/PUD which could have
valid previous entries. This requires proper
TLB maintanance on some architectures, like
ARM64.
Just to check, I take it that you mean we could have a valid table
entry, but all the entries in that next level table must be invalid,
right?
That was my assumption but my assumption can be wrong if any VA gets
block mapping for 1G directly (instead of the 2M cases we discussed
so far), then this would go for a toss.
Ok. Just considering the 4K -> 2M case, is that an assumption, or a
guarantee?
For 4K->2M case, that's confirmed. I mean, while mapping 2M, all the
next level entries will be unmapped and cleared. That gets ensured
before we land to page table code. But if someone calls these page table
APIs directly without respecting previous mappings, we will not hit
BUG_ON() anywhere but a crash later in unfamiliar situations. But that's
the wrong thing to do.
Thanks,
Mark.
Chintan
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