On Sat, Jan 13, 2018 at 10:51 AM, Linus Torvalds <torvalds@xxxxxxxxxxxxxxxxxxxx> wrote: > On Fri, Jan 12, 2018 at 4:15 PM, Tony Luck <tony.luck@xxxxxxxxx> wrote: > So your argument depends on "the uarch will actually run the code in > order if there are no events that block the pipeline". And might be bogus ... I'm a software person not a u-arch expert. That sounded good in my head, but the level of parallelism may be greater than I can imagine. > Or at least it depends on a certain latency of the killing of any OoO > execution being low enough that the cache access doesn't even begin. > > I realize that that is very much a particular microarchitectural > detail, but it's actually a *big* deal. Do we have a set of rules for > what is not a worry, simply because the speculated accesses get killed > early enough? > > Apparently "test a register value against a constant" is good enough, > assuming that register is also needed for the address of the access. People who do understand this are working on what can be guaranteed. For now don't make big plans based on my ramblings. -Tony
