Hi! > > So this is in that same category, but yes, it's inconvenient. > > Disagreed, violently. CPU has to execute the instructions I ask it to > execute, and if it executes *anything* else that reveals any information > about the instructions that have *not* been executed, it's flawed. I agree that's a flaw. Unfortunately... CPUs do execute instructions you did not ask them to execute all the time. Plus CPU designers forgot that cache state (and active row in DRAM) is actually observable side-effect. ....and that's where we are today. If you want, I have two systems with AMD Geode. One is PC. Neither is very fast. All the other general purpose CPUs I have -- and that includes smartphones -- are likely out-of-order, and that means flawed. So... situation is bad. CPUs do execute intruction you did not ask them to execute. I don't think that's reasonable to change. I believe "right" fix would be for CPUs to treat even DRAM read as side-effects, and adjust speculation accordingly. I'm not sure Intel/AMD is going to do the right thing here. Oh, I have an FPGA, too, if you want to play with RISC-V :-). Best regards, Pavel -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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