On Mon, Nov 27, 2017 at 1:28 PM, Greentime Hu <green.hu@xxxxxxxxx> wrote: > From: Rick Chen <rickchen36@xxxxxxxxx> > > Add a document to describe Andestech atcpit100 timer and > binding information. > > Signed-off-by: Rick Chen <rickchen36@xxxxxxxxx> > Acked-by: Rob Herring <robh@xxxxxxxxxx> > Signed-off-by: Greentime Hu <green.hu@xxxxxxxxx> Thanks for submitting this interesting architecture! (...) > +Required properties: > +- compatible : Should be "andestech,atcpit100" > +- reg : Address and length of the register set > +- interrupts : Reference to the timer interrupt > +- clocks : a clock to provide the tick rate for "andestech,atcpit100" > +- clock-names : should be "PCLK" for the external tick timer. This text seem wrong. PCLK is the internal timer, right? "PCLK" is "peripheral clock" (I hope) and that comes from the bus. Consider also adding an optional "EXTCLK" already now, since it is evident from the driver that this is also supported. Yours, Linus Walleij
