On May 26, 2017 8:51:48 AM PDT, Linus Torvalds <torvalds@xxxxxxxxxxxxxxxxxxxx> wrote: >On Fri, May 26, 2017 at 6:00 AM, Kirill A. Shutemov ><kirill@xxxxxxxxxxxxx> wrote: >> >> I don't see how kernel threads can use 4-level paging. It doesn't >work >> from virtual memory layout POV. Kernel claims half of full virtual >address >> space for itself -- 256 PGD entries, not one as we would effectively >have >> in case of switching to 4-level paging. For instance, addresses, >where >> vmalloc and vmemmap are mapped, are not canonical with 4-level >paging. > >I would have just assumed we'd map the kernel in the shared part that >fits in the top 47 bits. > >But it sounds like you can't switch back and forth anyway, so I guess >it's moot. > >Where *is* the LA57 documentation, btw? I had an old x86 architecture >manual, so I updated it, but LA57 isn't mentioned in the new one >either. > > Linus As one of the major motivations for LA57 is that we expect that we will have machines with more than 2^46 bytes of memory in the near future, it isn't feasible in most cases to do per-VM LA57. The only case where that even has any utility is for an application to want more than 128 TiB address space on a machine with no more than 64 TiB of RAM. It is kind of a narrow use case, I think. -- Sent from my Android device with K-9 Mail. Please excuse my brevity.
