Le 11/04/2017 à 14:28, Lorenzo Pieralisi a écrit : > The PCI specifications (Rev 3.0, 3.2.5 "Transaction Ordering and Posting") > mandate non-posted configuration transactions. As further highlighted in > the PCIe specifications (4.0 - Rev0.3, "Ordering Considerations for the > Enhanced Configuration Access Mechanism"), through ECAM and > ECAM-derivative configuration mechanism, the memory mapped transactions > from the host CPU into Configuration Requests on the PCI express fabric > may create ordering problems for software because writes to memory > address are typically posted transactions (unless the architecture can > enforce through virtual address mapping non-posted write transactions > behaviour) but writes to Configuration Space are not posted on the PCI > express fabric. > > Include the asm-generic ioremap_nopost() implementation (currently > falling back to ioremap_nocache()) to provide a non-posted writes > ioremap interface to kernel subsystems. > > Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx> > Cc: Bjorn Helgaas <bhelgaas@xxxxxxxxxx> > Cc: Hans-Christian Egtvedt <egtvedt@xxxxxxxxxxxx> > Cc: Haavard Skinnemoen <hskinnemoen@xxxxxxxxx> > --- > arch/avr32/include/asm/io.h | 1 + > 1 file changed, 1 insertion(+) You probably need to remove this one as the avr32 architecture will be removed in kernel 4.12: https://lkml.org/lkml/2017/3/27/422 Best regards, > diff --git a/arch/avr32/include/asm/io.h b/arch/avr32/include/asm/io.h > index f855646..b2ff522 100644 > --- a/arch/avr32/include/asm/io.h > +++ b/arch/avr32/include/asm/io.h > @@ -298,6 +298,7 @@ extern void __iounmap(void __iomem *addr); > #define ioremap_wc ioremap_nocache > #define ioremap_wt ioremap_nocache > #define ioremap_uc ioremap_nocache > +#include <asm-generic/ioremap-nopost.h> > > #define cached(addr) P1SEGADDR(addr) > #define uncached(addr) P2SEGADDR(addr) > -- Nicolas Ferre
