Most of things are in place and we can enable support of 5-level paging. MPX for 5-level paging will be enabled with separate patchset. It requires change to GCC components which has not ready yet. Signed-off-by: Kirill A. Shutemov <kirill.shutemov@xxxxxxxxxxxxxxx> --- arch/x86/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 3d51256a9e61..07cc4f27ca41 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -315,6 +315,7 @@ config DEBUG_RODATA config PGTABLE_LEVELS int + default 5 if X86_5LEVEL default 4 if X86_64 default 3 if X86_PAE default 2 @@ -1379,6 +1380,10 @@ config X86_PAE has the cost of more pagetable lookup overhead, and also consumes more pagetable space per process. +config X86_5LEVEL + bool "Enable 5-level page tables support" + depends on X86_64 + config ARCH_PHYS_ADDR_T_64BIT def_bool y depends on X86_64 || X86_PAE @@ -1737,6 +1742,7 @@ config X86_SMAP config X86_INTEL_MPX prompt "Intel MPX (Memory Protection Extensions)" def_bool n + depends on !X86_5LEVEL depends on CPU_SUP_INTEL ---help--- MPX provides hardware features that can be used in -- 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe linux-arch" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
