On Tue, Nov 08, 2016 at 10:08:37PM -0800, Linus Torvalds wrote: > On Tue, Nov 8, 2016 at 7:54 PM, Feng Tang <feng.tang@xxxxxxxxx> wrote: > > On Wed, Nov 02, 2016 at 04:47:37AM +0800, Ville Syrjälä wrote: > >> > >> I left the thing running for the weekend and it failed 26 out of 16057 > >> times with the 25ms timeout. Looks like it takes ~5 minutes to resume > >> when it fails, but eventually it does come back. > > > > Just came back from a travel. Yes, the 5 minutes delay may be due to the > > expiration of the HPET timer, counting from 0 to 0xffffffff for a 13M > > frequencey HPET takes about 300 seconds. After resume, it seems nobody > > arms it so my old patch forces to arm one event. > > Ville, what happens if you disable HPET? Can you force the TSC with > "clocksource=tsc" or "tsc=reliable". Does resume work reliably then? > > Or is this one of the CPU's where tsc just doesn't work? tsc=reliable allows use of the tsc it seems. Doesn't seem to help with resuming though. -- Ville Syrjälä Intel OTC -- To unsubscribe from this list: send the line "unsubscribe linux-arch" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
