On Thu, May 19, 2016 at 10:52:19AM +0100, David Howells wrote: > Peter Zijlstra <peterz@xxxxxxxxxxxxx> wrote: > > > Does this generate 'sane' code for LL/SC archs? That is, a single LL/SC > > loop and not a loop around an LL/SC cmpxchg. > I think the code it generates should look something like: > > test_atomic_add_unless: > .L7: > ldaxr w1, [x0] # __atomic_load_n() > cmp w1, 35 # } if (cur == unless) > beq .L4 # } break > add w2, w1, 86 # new = cur + addend > stlxr w4, w2, [x0] > cbnz w4, .L7 > .L4: > mov w1, w0 > ret > > but that requires the compiler to split up the LDAXR and STLXR instructions > and render arbitrary code between. Exactly. > I suspect that might be quite a stretch. > > I've opened: > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71191 > > to cover this. Thanks; until such time as this stretch has been made I don't see this intrinsic stuff being much use on any of the LL/SC archs. -- To unsubscribe from this list: send the line "unsubscribe linux-arch" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
