Hi Tony,
I recently took a look at the ia64 spinlock implementation in hope of
some inspiration regarding spin_unlock_wait, but I'm actually having
trouble understanding how spin_lock() guarantees ordering between taking
the lock and reads of some shared data in the critical section.
In particular, the loop where the locker spins awaiting its turn in the
queue:
for (;;) {
asm volatile ("ld4.c.nc %0=[%1]" : "=r"(serve) : "r"(p) : "memory");
if (!(((serve >> TICKET_SHIFT) ^ ticket) & TICKET_MASK))
return;
cpu_relax();
}
AFAIU, ld4.c.nc doesn't provide any ordering semantics, so a load to an
unrelated address from within the following critical section could be
speculated before we've actually acquired the lock.
What am I missing? Does the ALAT provide guarantees against other loads
somehow or does ld4.c.nc provide ordering guarantees that I didn't spot
in the manuals?
Cheers,
Will
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