On Mon, Aug 24, 2015 at 05:20:20PM +0300, Alexey Brodkin wrote:
> @@ -139,9 +141,11 @@ static int arc_pmu_event_init(struct perf_event *event)
> struct hw_perf_event *hwc = &event->hw;
> int ret;
>
> - hwc->sample_period = arc_pmu->max_period;
> - hwc->last_period = hwc->sample_period;
> - local64_set(&hwc->period_left, hwc->sample_period);
> + if (!is_sampling_event(event)) {
> + hwc->sample_period = arc_pmu->max_period;
> + hwc->last_period = hwc->sample_period;
> + local64_set(&hwc->period_left, hwc->sample_period);
> + }
So here we set a max_period sample period for !sampling events such that
we can properly deal with (short) counter overflow and accumulate into a
64bit value.
> switch (event->attr.type) {
> case PERF_TYPE_HARDWARE:
> @@ -243,6 +247,11 @@ static void arc_pmu_start(struct perf_event *event, int flags)
>
> arc_pmu_event_set_period(event);
>
> + /* Enable interrupt for this counter */
> + if (is_sampling_event(event))
> + write_aux_reg(ARC_REG_PCT_INT_CTRL,
> + read_aux_reg(ARC_REG_PCT_INT_CTRL) | (1 << idx));
> +
Yet here you fail to actually enable the interrupt for the non sampling
events, which makes the above not work.
> /* enable ARC pmu here */
> write_aux_reg(ARC_REG_PCT_INDEX, idx);
> write_aux_reg(ARC_REG_PCT_CONFIG, hwc->config);
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