On Tue, 2015-07-14 at 00:15 +0200, Peter Zijlstra wrote: > > This is instead the sequence that is of concern: > > > > store a > > unlock M > > lock N > > load b > > So its late and that table didn't parse, but that should be ordered too. > The load of b should not be able to escape the lock N. > > If only because LWSYNC is a valid RMB and any LOCK implementation must > load the lock state to observe it unlocked. What happens is that the load passes the store conditional, though it doesn't pass the load with reserve. However, both store A and unlock M being just stores with an lwsync, can pass a load, so they can pass the load with reserve. And thus inside the LL/SC loop, our store A has passed our load B. > > > Additionally, the assertion in Documentation/memory_barriers.txt that > > > the sequence above can be reordered as > > > > > > LOCK N > > > store b > > > store a > > > UNLOCK M > > > > > > is not true on any existing arch in Linux. > > > > It was at one time and might be again. > > What would be required to make this true? I'm having a hard time seeing > how things can get reordered like that. -- To unsubscribe from this list: send the line "unsubscribe linux-arch" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
