On Tue, Jun 23, 2015 at 10:52:06AM +0100, Vineet Gupta wrote: > ARCv2 based HS38 cores are weakly ordered and thus explicit barriers for > kernel proper. > > SMP barrier is provided by DMB instruction which also guarantees local > barrier hence used as backend of smp_*mb() as well as *mb() APIs > > Also hookup barriers into MMIO accessors to avoid ordering issues in IO > > Cc: Peter Zijlstra (Intel) <peterz@xxxxxxxxxxxxx> > Cc: Will Deacon <will.deacon@xxxxxxx> > Signed-off-by: Vineet Gupta <vgupta@xxxxxxxxxxxx> > --- > Changes since v2 > * lkml discussion link points to lkml redirector (PeterZ) > * Updated comment about IO ordering to use standard LD/ST (Will Deacon) > > Changes since v1 > * Better changelog and comments > * local/mandatory barriers to NOT use DSYNC, but DMB > * define DMB based mandatory barriers even for !SMP > --- [...] > +/* > + * MMIO can also get buffered/optimized in micro-arch, so barriers needed > + * Based on ARM model for the typical use case > + * > + * <ST [DMA buffer]> > + * wmb() > + * <writel MMIO "go" reg> > + * or: > + * <readl MMIO "status" reg> > + * rmb() > + * <LD [DMA buffer]> > + * > + * http://lkml.kernel.org/r/20150622133656.GG1583@xxxxxxx > + */ If that makes sense to you, then fine, but I find the wmb() and rmb() a bit odd since they're implied by the writel/readl macros. Regardless, you can keep my reviewed-by from last time. Will -- To unsubscribe from this list: send the line "unsubscribe linux-arch" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
