Hi Vineet, On Tue, Jun 23, 2015 at 08:58:03AM +0100, Vineet Gupta wrote: > ARCv2 based HS38 cores are weakly ordered and thus explicit barriers for > kernel proper. > > SMP barrier is provided by DMB instruction which also guarantees local > barrier hence used as backend of smp_*mb() as well as *mb() APIs > > Also hookup barriers into MMIO accessors to avoid ordering issues in IO > > Cc: Peter Zijlstra (Intel) <peterz@xxxxxxxxxxxxx> > Cc: Will Deacon <will.deacon@xxxxxxx> > Signed-off-by: Vineet Gupta <vgupta@xxxxxxxxxxxx> > --- > Changes since v1 > * Better changelog and comments > * local/mandatory barriers to NOT use DSYNC, but DMB > * define DMB based mandatory barriers even for !SMP > --- Functionally, all looks good to me. However, my comment is completely misleading ;) > +/* > + * MMIO can also get buffered/optimized in micro-arch, so barriers needed > + * Based on ARM model for the typical use case > + * > + * <writel_relaxed DMA buffer> > + * <writel MMIO "go" reg> > + * or: > + * <readl MMIO "status" reg> > + * <readl_relaxed DMA buffer> The writel_relaxed/readl_relaxed parts here would actually just be bog-standard loads and stores to an in-memory buffer. I was trying too hard to show the barrier semantics and accidentally turned the DMA buffers into __iomem regions. If you fix the comment: Reviewed-by: Will Deacon <will.deacon@xxxxxxx> Sorry for messing you about. Will -- To unsubscribe from this list: send the line "unsubscribe linux-arch" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
