On Tuesday 09 June 2015 06:05 PM, Peter Zijlstra wrote: On Tue, Jun 09, 2015 at 05:18:22PM +0530, Vineet Gupta wrote: This really really wants a Changelog describing the actual hardware fail and why this workaround is sufficient. OK - I need some more time to rehash the exact details with our hardware folks. But AFAIKR, this was hardware livelock in llock/scond when 2 cores were doing r-m-w to two different words in the same cache line - adding prefetchw (prefetch with a write intent) would get the line in exclusive state and break the livelock. The test itself was one from EEMBC Multibench but I'll have to look it up. Wasn't there something similar in ARM world too - they have some sort of snoop-delayed exclusive handling in hardware to mitigate something similar although as Will later remarked it involved llock/scond with vanilla ld/st to same line/word ? http://lists.infradead.org/pipermail/linux-arm-kernel/2014-May/254142.html Thx, -Vineet -- To unsubscribe from this list: send the line "unsubscribe linux-arch" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
