At Wed, 21 Jan 2015 12:02:14 +0100,
Geert Uytterhoeven wrote:
>
> On Wed, Jan 21, 2015 at 5:23 AM, Yoshinori Sato
> <ysato@xxxxxxxxxxxxxxxxxxxx> wrote:
> > --- /dev/null
> > +++ b/arch/h8300/include/asm/cache.h
> > @@ -0,0 +1,13 @@
> > +#ifndef __ARCH_H8300_CACHE_H
> > +#define __ARCH_H8300_CACHE_H
> > +
> > +/* bytes per L1 cache line */
> > +#define L1_CACHE_SHIFT 2
> > +#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
> > +
> > +/* m68k-elf-gcc 2.95.2 doesn't like these */
>
> Please drop the above comment.
OK.
fix V2 patch.
>
> > +
> > +#define __cacheline_aligned
> > +#define ____cacheline_aligned
> > +
> > +#endif
>
> > --- /dev/null
> > +++ b/arch/h8300/include/asm/io.h
> > @@ -0,0 +1,355 @@
> > +#ifndef _H8300_IO_H
> > +#define _H8300_IO_H
> > +
> > +#ifdef __KERNEL__
> > +
> > +/*
> > + * These are for ISA/PCI shared memory _only_ and should never be used
> > + * on any other type of memory, including Zorro memory. They are meant to
> > + * access the bus in the bus byte order which is little-endian!.
> > + *
> > + * readX/writeX() are used to access memory mapped devices. On some
> > + * architectures the memory mapped IO stuff needs to be accessed
> > + * differently. On the m68k architecture, we just read/write the
> > + * memory location directly.
> > + */
> > +/* ++roman: The assignments to temp. vars avoid that gcc sometimes generates
> > + * two accesses to memory, which may be undesirable for some devices.
>
> I doubt all of the above is relevant for h8300.
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
--
Yoshinori Sato
<ysato@xxxxxxxxxxxxxxxxxxxx>
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