On Tue, Nov 18, 2014 at 04:20:46PM +0000, Alexander Duyck wrote: > On 11/18/2014 03:58 AM, Will Deacon wrote: > > So actually, this is an interesting case where the barrier would like to > > know whether the memory returned by dma_alloc_coherent is h/w coherent > > (normal, cacheable) or s/w coherent (normal, non-cacheable). I think Ben > > is thinking of the h/w coherent case (i.e. actual snooping into the CPU > > caches by the DMA master). > > > > For the former, we could use inner-shareable barriers. For the latter, we'd > > need to use outer-shareable barriers. > > > > If we can't tell, then these should be dmb(osh), which will work for both. > > > > Okay, so I will update the ARM portion of my patches to use osh and > oshst then since it sounds like I was using too strong of barriers. Sounds good. Another reason this is interesting is because the native acquire/release instructions on ARMv8 actually take into account the shareability domain of the virtual address, so using them would give you the shareability domain you want but slightly stronger ordering guarantees within that domain. Still, either of them will be a damn sight better than the dsb we currently have courtesy of the mandatory barriers. Will -- To unsubscribe from this list: send the line "unsubscribe linux-arch" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
