On 25/09/14 16:15, Arnd Bergmann wrote:
> On Thursday 25 September 2014 17:07:47 Arnd Bergmann wrote:
>
>> The current version doesn't let you do that, so I'll keel the #ifdef
>> sections separate. This also means that I won't apply your patch 17:
>> we will keep needing the #ifdef to support all three relevant combinations:
>>
>> a) architectures that provide neither and want to get the defaults
>> from asm-generic
>> b) architectures that provide the non-relaxed versions and want tog
>> to get just the relaxed version from asm-generic
>> c) architectures that provide both
>>
>
> And here is the new version I applied:
>
> diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h
> index 508a57257de5..3e976be3bdd4 100644
> --- a/include/asm-generic/io.h
> +++ b/include/asm-generic/io.h
> @@ -174,6 +174,43 @@ static inline void writeq(u64 value, void __iomem *addr)
> #endif /* CONFIG_64BIT */
>
> /*
> + * {read,write}{b,w,l,q}_relaxed() are like the regular version, but
> + * are not guaranteed to provide ordering against spinlocks or memory
> + * accesses.
> + */
> +#ifndef readb_relaxed
> +#define readb_relaxed readb
> +#endif
> +
> +#ifndef readw_relaxed
> +#define readw_relaxed readw
> +#endif
> +
> +#ifndef readl_relaxed
> +#define readl_relaxed readl
> +#endif
> +
> +#ifndef readq_relaxed
> +#define readq_relaxed readq
> +#endif
Not really sure if it matters but this gives a rather surprising
behaviour to #ifdef readq_relaxed given that readq may not be defined.
> +
> +#ifndef writeb_relaxed
> +#define writeb_relaxed writeb
> +#endif
> +
> +#ifndef writew_relaxed
> +#define writew_relaxed writew
> +#endif
> +
> +#ifndef writel_relaxed
> +#define writel_relaxed writel
> +#endif
> +
> +#ifndef writeq_relaxed
> +#define writeq_relaxed writeq
> +#endif
Ditto.
> +
> +/*
> * {read,write}s{b,w,l,q}() repeatedly access the same memory address in
> * native endianness in 8-, 16-, 32- or 64-bit chunks (@count times).
> */
>
>
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