Hi Will,
On Tue, Apr 22, 2014 at 05:08:21PM +0100, Will Deacon wrote:
> On Thu, Apr 17, 2014 at 02:44:19PM +0100, Will Deacon wrote:
> > write{b,w,l,q}_relaxed are implemented by some architectures in order to
> > permit memory-mapped I/O accesses with weaker barrier semantics than the
> > non-relaxed variants.
> >
> > This patch adds dummy macros for the write accessors to x86, in the
> > same vein as the dummy definitions for the relaxed read accessors.
[...]
> > --- a/arch/x86/include/asm/io.h
> > +++ b/arch/x86/include/asm/io.h
> > @@ -74,6 +74,9 @@ build_mmio_write(__writel, "l", unsigned int, "r", )
> > #define __raw_readw __readw
> > #define __raw_readl __readl
> >
> > +#define writeb_relaxed(v, a) __writeb(v, a)
> > +#define writew_relaxed(v, a) __writew(v, a)
> > +#define writel_relaxed(v, a) __writel(v, a)
> > #define __raw_writeb __writeb
> > #define __raw_writew __writew
> > #define __raw_writel __writel
[...]
>
> Actually, I should be using the regular (i.e. without the double underscore
> prefix) accessors for the relaxed variants, including the existing read
> flavours here. The proposed semantics are that the accessors are ordered
> with respect to each other, which necessitates a compiler barrier.
Are you planning on resubmitting this series? I've run into several
situations in which I can't compile-test a driver on a different ARCH
just because of this issue.
Thanks,
Brian
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