On Thu, Nov 07, 2013 at 04:03:20PM -0500, Mathieu Desnoyers wrote:
> * peterz@xxxxxxxxxxxxx (peterz@xxxxxxxxxxxxx) wrote:
> > +#define smp_store_release(p, v) \
> > +do { \
> > + compiletime_assert_atomic_type(*p); \
> > + __lwsync(); \
>
> Even though this is correct, it appears to bear more overhead than
> necessary. See arch/powerpc/include/asm/synch.h
>
> PPC_ACQUIRE_BARRIER and PPC_RELEASE_BARRIER
>
> You'll notice that some variants of powerpc require something more
> heavy-weight than a lwsync instruction. The fallback will be "isync"
> rather than "sync" if you use PPC_ACQUIRE_BARRIER and
> PPC_RELEASE_BARRIER rather than LWSYNC directly.
I think this needs to fall back to sync as Peter has it. isync is not
actually a memory barrier. It is more like an execution barrier, and
when used after stwcx.; bne (or stdcx.; bne) it has the effect of
preventing following loads/stores from being executed until the
stwcx. has completed. In this case we're not using stwcx./stdcx.,
just a normal store, so isync won't have the desired effect.
Regards,
Paul.
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