On Tue, 17 Sep 2013, Geert Uytterhoeven wrote:
> On Tue, Sep 17, 2013 at 8:53 PM, Thomas Gleixner <tglx@xxxxxxxxxxxxx> wrote:
> > --- linux-2.6.orig/arch/m68k/include/asm/hardirq.h
> > +++ linux-2.6/arch/m68k/include/asm/hardirq.h
> > @@ -5,17 +5,6 @@
> > #include <linux/cache.h>
> > #include <asm/irq.h>
> >
> > -#define HARDIRQ_BITS 8
>
> > --- linux-2.6.orig/include/linux/preempt_mask.h
> > +++ linux-2.6/include/linux/preempt_mask.h
> > @@ -11,36 +11,22 @@
> > * - bits 0-7 are the preemption count (max preemption depth: 256)
> > * - bits 8-15 are the softirq count (max # of softirqs: 256)
> > *
> > - * The hardirq count can in theory reach the same as NR_IRQS.
> > - * In reality, the number of nested IRQS is limited to the stack
> > - * size as well. For archs with over 1000 IRQS it is not practical
> > - * to expect that they will all nest. We give a max of 10 bits for
> > - * hardirq nesting. An arch may choose to give less than 10 bits.
> > - * m68k expects it to be 8.
>
> m68k needs some changes in arch/m68k/kernel/entry.S, cfr. this check
> in arch/m68k/kernel/ints.c:
>
> /* assembly irq entry code relies on this... */
> if (HARDIRQ_MASK != 0x00ff0000) {
> extern void hardirq_mask_is_broken(void);
> hardirq_mask_is_broken();
> }
>
> Haven't looked into the details yet...
Whee. Did not notice that one. Though I can't find anything
interesting in the low level entry code... Looks like some more
histerical left overs.
Thanks,
tglx
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