On Wed, 4 Sep 2013, Will Deacon wrote:
> Hmm, why can't you get interrupted during atomic64_xchg? On ARM, we have the
> following sequence:
AFAICT atomic means one uninterruptible action.
> static inline u64 atomic64_xchg(atomic64_t *ptr, u64 new)
> {
> u64 result;
> unsigned long tmp;
>
> smp_mb();
>
> __asm__ __volatile__("@ atomic64_xchg\n"
> "1: ldrexd %0, %H0, [%3]\n"
> " strexd %1, %4, %H4, [%3]\n"
> " teq %1, #0\n"
> " bne 1b"
> : "=&r" (result), "=&r" (tmp), "+Qo" (ptr->counter)
> : "r" (&ptr->counter), "r" (new)
> : "cc");
>
> smp_mb();
>
> return result;
> }
>
> which relies on interrupts clearing the exclusive monitor to force us back
> around the loop in the inline asm. I could imagine other architectures doing
> similar, but only detecting the other writer if it used the same
> instructions.
Well I have never done ARM asm but this looks vaguely like a cmpxchg loop?
That would either perform an atomic change or fail and retry?
If so it still fits the definition of atomic. The change or fail operation
is atomic.
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